1. Field of the Invention
The invention is related to the field of communications, and in particular, to integrated circuits that process communication packets.
2. Statement of the Problem
Communications systems transfer information in packet streams. The packets in the streams each contain a header and a payload. The header contains control information, such as addressing or channel information, that indicate how the packet should be handled. The payload contains the information that is being transferred. Some packets are broken into segments for processing. The term xe2x80x9cpacketxe2x80x9d is intended to include packet segments. Some examples of packets include, Asynchronous Transfer Mode (ATM) cells, Internet Protocol (IP) packets, frame relay packets, Ethernet packets, or some other packet-like information block.
An integrated circuit known as a stream processor has been developed recently to address the special needs of packet communication networking. Traffic stream processors are designed to apply robust functionality to extremely high-speed packet streams. This dual design requirement is often in conflict because the high-speeds limit the level of functionality that can be applied to the packet stream.
Robust functionality is critical with today""s diverse but converging communication systems. Stream processors must handle multiple protocols and interwork between streams of different protocols. Stream processors must also ensure that quality-of-service constraints are met with respect to bandwidth and priority. Each stream should receive the bandwidth allocation and priority that is defined in corresponding service level agreements. This functionality must be applied differently to different streams-possibly thousands of different streams.
To provide such functionality, a RISC-based core processor was developed with its own network-oriented instruction set. The instruction set is designed to accomplish common networking tasks in the fewest cycles. The core processor executes software applications built from the instruction set to apply the robust functionality to high-speed packet streams.
Unfortunately, the core processor must constantly determine which packet stream to handle next. Given the high-speeds of the packet streams, this function places a heavy burden on the core processor and expends critical processing capacity. Instead of providing additional quality-of-service processing, the core processor spends time deciding which packets to process.
The invention helps solve the above problems with an integrated circuit that processes communication packets and can function as a traffic stream processor. The integrated circuit uses co-processor circuitry to establish a prioritized work queue for the core processor. The core processor can simply process packets from the work queue and avoid expending capacity to determine a prioritized processing order. The capacity savings can be used to handle higher-speed streams or increase the available functionality.
The integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.
In some examples of the invention, the co-processor circuitry determines the prioritized processing order based on an availability of resources required by the core processor to process the communication packets or external requests to process the communication packets. The co-processor circuitry may select scheduling algorithms based on an internal scheduling state bits and use the selected scheduling algorithms to determine the prioritized processing order.
In some examples of the invention, the co-processor circuitry determines priorities for the communication packets, places entries in priority queues based on the priorities, and arbitrates the entries to establish the prioritized processing order. The co-processor circuitry may determine the priorities based on an individual weight for each of the priority queues that guarantees a percentage of core processor bandwidth. The co-processor circuitry may determine the priorities based on a number of outstanding requests for processing from individual ones of the priority queues.
In some examples of the invention, the co-processor circuitry includes data buffers and context buffers. The co-processor circuitry correlates the communication packets with channel descriptors, transfers the channel descriptors from off-chip memory to the context buffers, and determine associations between the data buffers and the context buffers to maintain the correlation between the communication packets and the channel descriptors. The core processor processes the packets in the data buffers based on the prioritized processing order and the associations between the data buffers and the context buffers. The data buffers may each be of a fixed size that is small enough to hold only a single ATM cell, packet, or packet segment. The co-processor circuitry selects correlation algorithms based on an internal correlation state bits and uses the selected correlation algorithms to correlate the communication packets with the channel descriptors.